There is a continuing trend towards increasing the capacity of DRAMS. Such an increase in capacity is best achieved by decreasing the surface area of the memory cells and increasing their packing density to increase the number of memory cells in the semiconductor body (silicon chip) that houses the DRAM. The reduction in surface area and increase in packing density can be achieved by both a decrease in the feature sizes of the elements of the DRAM, and by the use of transistors, capacitors, and interconnect structures which are three-dimensional in nature, with their active elements lying not only on the surface of the semiconductor body, but also extending down into the interior of the semiconductor body.
One technique which has been used to increase the packing density of the memory cells has been to use a vertical trench in which is formed a capacitor that serves as a storage element of the memory cell. A further technique has been to use as the access transistor a vertical channel transistor formed on the sidewall of the vertical trench in which the capacitor is formed.
FIG. 1 shows the elements of a well known prior art DRAM memory cell comprising a field effect transistor 130 and a capacitor 140. Transistor 130 has a first output 133 connected to a first plate 141 of the capacitor 140 whose second plate is connected to a common potential, typically ground potential. A connection between the output 133 and the capacitor plate 141 is made by means of an interconnection structure 150. A second output 131 of the transistor 130 is connected to a bit line 110, and a gate (control electrode) 132 of the transistor 130 is connected to a word line 120. Multiple bit lines, of which bit line 110 is one, run vertically through an array of the memory cells, and multiple word lines, of which word line 120 is one, run horizontally through the array of memory cells.
Traditionally, the transistors 130 and capacitors 140 were formed as planar devices on the surface of a semiconductor body.
FIG. 2 shows schematically the cross-section of a prior art implementation of a transistor-capacitor DRAM memory cell in which a storage capacitor 240 is formed in a lower portion of a vertical trench 260 in a semiconductor 200, and a transistor 230, which comprises a first output region 231, a second output region 233, and a gate 232, has a channel region 235 formed on a sidewall 236 in an upper portion of the vertical trench 260. In a typical embodiment semiconductor body 200 is of p-type conductivity. A relatively thick silicon dioxide insulting layer 261 is formed on a major portion 265 of a surface of the trench 260. At a bottom of the trench 260 the thick oxide layer 261 is replaced with a thinner oxide layer 243. On sidewall 236 of the surface of an upper portion of the trench 260 a thin gate oxide layer 234 is formed, and serves as the gate oxide of the transistor 230. A portion 263 of the oxide layer 261 has been removed. A lower portion of the trench 260 has been filled up to a level above the thinner oxide layer 243, and above the opening 263, with a conducting material, typically highly-doped polysilicon of n-type conductivity, which forms the first plate 241 of the capacitor 240. The second plate 242 of the capacitor 240 is formed by the semiconductor body 200. A top surface 244 of capacitor plate 241 is covered with a thick oxide layer 262. N-type dopant material diffuses from the capacitor plate 241 through the opening 263 into the semiconductor body 200 to form an n-type semiconductor region 233 which serves as the second output region 233 of the transistor 230. The portion of the trench 260 above the oxide layer 262 is filled with a conducting material, typically n-type polysilicon, to form a gate electrode 232 of the transistor 230. The first output region 231 is formed on a top surface 202 of the semiconductor body 200 and in one embodiment is of n-type conductivity. A word line 220 is formed on the surface 223 of the insulator layer 222 and contacts gate electrode 232 through an opening 221 in layer 222. A bit line 210 is formed on the surface 213 of the insulator layer 212 and contacts the second output region 231 through an opening 211 in layers 222 and 212.
The structure depicted in FIG. 2 implements the memory cell depicted in FIG. 1 in a three-dimensional structure with a conservative use of surface area of the semiconductor body 200.
FIG. 3 shows a sectional view, through the plane 3—3 of FIG. 2, of an array of prior art memory cells. A portion of each of four trenches, 260-1, 260-2, 260-3, and 260-4 of an array of such trenches are shown. A portion of the surface of each trench is covered with the thick oxide layers 261-1, 2, 3, and 4. The trenches have been filled with conductors 241-1, 2, 3, and 4. During processing a portion of the n-type dopant of the conductors 241-1, 2, 3, and 4 diffuses through the opening 263-1, 2, 3, and 4 (not shown) and forms the output regions 233-1, 2, 3, and 4 of the transistors.
It can be seen from the drawing that output regions 233-1, 233-2, 233-3, and 233-4 extend beyond the perimeter of the trenches themselves, and, in the case of output regions 233-1 and 233-3, are considerably closer to each other than are the trenches 260-1 and 260-3 themselves. The limiting factor in determining how close to each other the trenches can be placed is a minimum allowable distance between the output regions 233-1, 2, 3, and 4, rather than the minimum feature size of the lithographic and etching technologies. The minimum allowable distance between the output regions 233-1, 2, 3, and 4 is determined by considerations of leakage and performance of the memory cells. The distance between the output regions 233-1, 2, 3, and 4 is further influenced by variations in the out-diffusion of the dopant material and the voltage of the output region with respect to the semiconductor body. If two output regions become close enough, leakage current can flow between the two output regions. This can lead to failure of the memory array.
It is desirable to have a DRAM comprising an array of memory cells each having a vertical IGFET and a capacitor formed in a trench which has greater packing density than conventional DRAMs with high yields.